1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a word line decoder and high-speed disturb testing method, which is for the purpose of reducing the time required for the disturb test.
2. Description of the Related Art
The development of a semiconductor fabrication technique realizes smaller but more complicated circuits. Thus, a memory device is becoming more dense as the number of memory cell per unit area is increased. However, this plane and vertical decrease of the memory device requires more complicated and precise fabrication process, and thus the memory device accomplished by this process needs a complicated test requiring longer time in order to guarantee its reliability and quality. Practically, the performance of a memory device cannot be guaranteed even though its memory cell passes a test of reading or writing data "1" or "0". Complicated and densely arranged memory cells of a highly integrated memory device may become poor due to the interaction between them. How much the interaction affects the memory device depends on various causes such as memory structure, addressing circuit, the amount of substrate resistance, characteristic and structure of a memory cell or variation in the fabrication process. As a result, defects in memory devices appear in various types, and a test for screening these defects becomes various and complicated. This requires longer test time.
As a typical memory testing method, march test or checker board test is known. The disturb test shown in FIG. 1 approves itself effective for screening the defects of DRAM, and thus it is widely used. The disturb test can screen the soft error which inverts data of neighboring cell from "1" to "0" in case that all memory cells are functionally normally operated but have the disturb as shown in FIG. 1, which means repeatedly accessing the same address data. The most important condition of the disturb test is that a word line is repeatedly activated when data "0" is stored in the disturb cell and its neighboring cells have data "1".
FIG. 2 is a cross-sectional view showing the mechanism of the disturb test. Referring to FIG. 2, when a silicon pit 20 is generated in a gate oxide 10 due to a particle, transistors are normally operated but electron impact ionization occurs according to a high electric field in the silicon pit, to thereby generate holes and electrons. These holes move toward a substrate 100, and produce an ohmic drop in the substrate. Then, a substrate voltage partially increased according to the ohmic drop makes a bit line 30 grounded at 0V forward bias. By doing so, minor carriers of electrons are injected from bit line 30 into substrate 100. Thereafter, the electrons are transmitted and united with holes in a neighboring cell having data "1", thereby generating a cell leakage current. As a result, the soft error is induced. Furthermore, in case that the disturb is applied for a longer time, the gradual propagation of the error in a radial manner can be easily explained with regard to the fact that the electrons injected from the bit line are radially diffused.
As described above, the disturb test is based on the fact that the bit line becomes forward-biased according to the partial increase of the substrate voltage in case that the word line is repeatedly activated at a state that a predetermined data pattern is maintained. Here, it should be noted that poor cells are locally produced, and two poor cells having a distance from each other do not interfere to each other. Moreover, it is important that the word line is activated without regard to reading and writing data "0".
However, in the aforementioned conventional disturb test, the time required for the test is very long because the same word line should be repeatedly activated. It is desirable that test time becomes short in order to secure competitiveness in the highly integrated memory device production. In the fabrication of the semiconductor memory device, its fabrication cost is fixed owing to the development of the fabrication process regardless of increase in integration. However, the increased integration also increases the number of cell to be tested, and thus the test time becomes longer. This raises the cost required for the test.
Practically, in case that the aforementioned disturb test is applied for a highly integrated memory device such as 64M or 256M DRAM, the total test time is so long that the test is difficult to apply in terms of its fabrication cost. On the other hand, in the highly integrated memory device, since the density of its memory cells is increased, the same kind of error occurs frequently.